The present disclosure relates to phase locked loop (PLL) circuits and in particular to circuitry for detecting when the output of the PLL has locked onto a reference signal.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Phase locked loops (PPLs) are widely used in communications electronics and digital electronics. In wireless products, PLLs are typically used to generate high speed system clocks. When the electronics for a PLL are powered up, it can take on the order of tens of microseconds for the frequency of the PLL output signal to become stable. A lock detector circuit is typically provided to detect when the frequency of the PLL output signal has settled. The lock detector can generate a lock signal that can be used by the system for clock gating.
A typical PLL circuit configuration is illustrated in FIG. 1. The main blocks of a PLL circuit 100 typically include a phase frequency detector 112, a charge pump 114, a low-pass filter 116, a voltage controlled oscillator (VCO) 118, and a feedback counter 120. The phase frequency detector 112 detects the difference in phase and frequency between a reference signal (clock) Fref and a feedback signal (clock) Ffb, and generates an “up” (U) or a “down” (D) control signal based on whether the frequency of the feedback signal Ffb (feedback frequency) is lagging or leading the frequency of the reference signal Fref (reference frequency).
The phase frequency detector 112 outputs these “up” and “down” signals to the charge pump 114. If the charge pump receives an “up” signal, current is driven into the low-pass filter 116. Conversely, if the charge pump 114 receives a “down” signal, current is drawn from the low-pass filter 116. The low-pass filter 116 converts these signals to a control voltage (a DC level) that is used to control the VCO 118.
Based on the control voltage, a PLL output signal Fo of the VCO 118 oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback signal Ffb. Thus, if the phase detector 112 produces an “up” s signal, then the frequency of PLL output signal Fo increases. A “down” signal decreases the frequency of the PLL output signal Fo. The output of the VCO 118 stabilizes once the reference signal Fref and the feedback signal Ffb have the same phase and frequency. When the reference signal Fref and the feedback signal Ffb are aligned, the PLL output signal Fo is referred to variously as “locked,” “locked to the reference signal,” and the like.
A divide-by-N counter 120 may be inserted in the feedback loop to increase an amplitude of the PLL output signal Fo above the reference signal Fref. The PLL output signal Fo is equal to N times the reference signal Fref.
A lock detector 102 compares the reference signal Fref and the feedback signal Ffb to determine when a lock condition has occurred. A lock signal is output when the lock condition has occurred.
FIG. 1 further illustrates a simple timing chart. When power is applied to the circuitry at time t0, the frequency of the PLL output signal Fo begins to increase. During a period of time between t0 and t1, the PLL frequency is not unstable and cannot be used by the system. At time t1, the PLL frequency has stabilized, but typically a period of time (t2−t1) is allowed to pass to ensure that the PLL output signal Fo has fully settled. Accordingly, during the period of time between t0 and t2, the lock signal remains “LO”. At time t2, the lock signal goes “HI” to signify that the PLL output signal Fo is ready to clock the system logic.
FIG. 2 illustrates a conventional implementation for the lock detector 102 which determines signal lock based on the rising edges of the reference signal Fref and the feedback signal Ffb. The lock detector comprises two flip flop circuits, such as the flip flops 202 and 204. The reference signal Fref is delayed by an inverted delay line 206, and the delayed signal Fref′ feeds into the flip flop 202. The feedback signal Ffb clocks the flip flop 202. Similarly for the flip flop 204, the feedback signal Ffb is delayed by an inverted delay line 208, and the delayed signal Ffb′ feeds into the flip flop 204. The feedback signal Fref clocks the flip flop 204. The outputs of the flip flops 202 and 204 feed into NAND gate 210.
A timing circuit 212 comprises a capacitor 222 that is charged by a current source 224. So long as transistor 228 remains in the OFF condition, then after a certain amount of time proportional to I/C, where I is the current and C is the capacitance, the capacitor 222 will charge to a voltage level (i.e., a threshold voltage level) sufficient to trigger a buffer 228 and output a signal that constitutes the lock detect signal. The transistor 228 is controlled by the output of the NAND gate 210. During power up, the phase between the reference signal Fref and the feedback signal Ffb will vary until the feedback signal attains a lock with the reference signal.
Referring to FIG. 3, a timing diagram of the reference signal Fref and the feedback signal Ffb is illustrated for the lock condition. In this and subsequent figures, the shaded areas in the timing diagrams represent prior output states (“HI” or “LO”) that depend on the previous phase relation of the signals Fref and Ffb. The flip flops 202 and 204 shown in FIG. 2 are clocked on the rising edges of Ffb and Fref respectively. Accordingly, the flip flops will latch respective inverted signals Fref′ and Ffb′ delayed by τ (the propagation delay of inverted delay lines 206 and 208). As can be seen, in the lock condition depicted in FIG. 3, the rising edges of the reference signal Fref and the feedback signal Ffb are aligned. The flip flop outputs Q202 and Q204 are “HI”, and consequently the output of NAND gate 210 is “LO”. Thus, the transistor 228 is OFF and will remain in the OFF state so long as the lock condition exists, allowing the capacitor 222 to continue charging and the lock detect signal asserted.
Referring to FIG. 4, a timing diagram is illustrated for a “no lock” condition where the reference signal Fref and the feedback signal Ffb are not in phase. The timing diagram shows that the output of flip flop 202 is “LO” because of the timing of the rising edge of Ffb relative to the inverted and delayed reference signal Fref′. Accordingly, the NAND gate 210 is “HI” for this condition. The transistor 228 is turned ON and consequently the capacitor 222 does not charge.
Referring to FIG. 5, a timing diagram is illustrated for a “no lock” condition, where the phase relation between the reference signal Fref and the feedback signal Ffb create a condition at time tx that causes the NAND gate 210 to incorrectly outputs a “LO” logic level. The “LO” output of the NAND gate 210 turns OFF the transistor 228, allowing the capacitor 222 to charge and the lock detect signal to erroneously assert.